1. Field of the Invention
The present invention relates to a test head for use in an electrical characteristic test of a plurality of integrated circuits formed on a semiconductor wafer.
2. Description of the Prior Art
Generally, as shown in FIGS. 7 and 8, a plurality of integrated circuits 12 are formed on a semiconductor wafer 10 in a matrix array. Each of the integrated circuits has a square form and has a plurality of electrode portions, i.e., electrode pads 14, formed on each edge portion corresponding to each side of the square. The integrated circuits 12 constituting each row and each column of the matrix are in a straight line.
Such integrated circuits are subjected to electricity-loaded tests (electrical characteristic tests) as to whether the circuits function as designated in specifications. Such tests are generally carried out using a testing head, i.e., a test head, generally called a probe card, probe board, or the like.
If units of the integrated circuits are tested unit by unit in such an electricity-loaded test, it takes a long time to carry out the test on all of the integrated circuits formed on one wafer. Therefore, it is desired that a plurality of integrated circuits are tested at the same time in such electricity-loaded tests.
In the gazette of Japanese Patent Apple. Public Disclosure No. 1-201166, there are disclosed two types of test heads for testing (inspecting) at the same time a plurality of integrated circuits successively arranged in alignment with the row or column of a matrix array. One type of the heads is provided with a plurality of probes disposed on a plate-like member with a rectangular opening formed in its center. The other type of the heads is provided with a plurality of probes disposed on two plate-like members, each having a rectangular opening formed in the center, in which both the plate-like members are piled up such that probes of both of the plate-like members cross each other.
In the one type of the heads, the probes disposed at the edge portions of the opening in the lengthwise direction are put in contact with pads in the direction of the array of integrated circuits to be tested and the probes disposed at the edge portions of the opening in the widthwise direction are put into contact with pads in the direction perpendicular to the direction of the array of the integrated circuits. In such a head, since a great number of probes for a plurality of integrated circuits must be disposed at the edge portions of the opening in the lengthwise direction, probes to be disposed at the edge portion of the opening in the lengthwise direction becomes too many. As a result, it is difficult to correctly connect the probes to their respective wiring portions and, hence, wrong connection between the probe and the wiring portion is frequently made.
In the case of the other type of the heads, the probes disposed on one plate-like member at the edge portions of its opening in the lengthwise direction are put into contact with pads arranged in the direction of the array of integrated circuits to be tested and the probes disposed on the other plate-like member at the edge portions of its opening in the lengthwise direction are put into contact with pads arranged in the direction perpendicular to the array of the integrated circuits. In such a head, however, since the probes of both the plate-like members cross each other, it is difficult to dispose the probes on the plate-like members without causing the probes of both the plate-like members to contact each other and to assemble both the plate-like members into a unit.
An object of the present invention is to prevent the probes from contacting each other and facilitate the connection work of the probes to the wiring portions and the fabrication of the heads.